The present invention relates to a semiconductor device having an insulated gate power MOSFET in which a gate electrode is formed in a recessed trench formed from the surface of a semiconductor layer, so-called transistor cells of a trench structure are arranged in a matrix form. More specifically, the invention relates to a semiconductor device having a MOSFET improved in gate dielectric breakdown voltage by forming a gate pad contacted with a gate wiring inside a recessed part etched from the semiconductor layer surface as similar to the recessed trench formed with the gate electrode.
A high-power gate-driven MOS transistor of a traditional trench structure adopts a structure where many transistor cells are arranged in a matrix form for the realization of heavy current. For example, as shown in FIG. 8A of a partially sectional illustration, an n-type semiconductor layer (epitaxial growth layer) 21 to be a drain region is epitaxially grown over an n+-type semiconductor substrate 21a. A recessed trench is formed in the semiconductor layer 21 in a grid form. A gate oxide 24 is deposited over the inner surface, and polysilicon to be a gate electrode 25 is buried. Then, a p-type channel diffusion region 22 is formed in the semiconductor layer 21 therearound, and an n+-type source region 23 is formed around on the gate electrode 25 side, whereby a channel region 22a is formed vertically as having contact with the gate oxide 24. Furthermore, a contact hole is formed in an insulating film 26 comprised of SiO2; the insulating film is formed over the surface. A source wiring 27 is formed so as to have Ohmic contact with the exposed source region 23 and channel diffusion region 22. A drain electrode 28 is formed on the backside of the semiconductor substrate 21a. 
The gate electrode 25 described above is comprised of polysilicon and is not formed into fully low resistance. Therefore, as depicted in FIG. 8B of a plan illustration showing an example of a gate wiring 29 of a semiconductor chip, it is formed in which the gate wiring of a metal film comprised of A1 is partially connected around a transistor cell region 30 or inside the cell region 30 so as not to increase resistance in cells remote from a wire bonding part 29a . To contact the polysilicon film with the metal film formed of Al, as shown in FIG. 8C of a partially sectional illustration showing the portion of the gate wiring 29, a gate pad 25a is formed on the semiconductor layer surface continuously to the gate electrode 25 through a gate oxide (not shown). The gate wiring 29 is formed above the gate pad 25a through an insulating film 31 (the insulating film is also formed on the left side in the drawing, but it is omitted in the drawing). In addition, as shown in FIG. 8B, there is also the case where the gate wiring called a gate finger 29b is disposed in the cell region 30 in places, but the case has the same structure as well. In FIG. 8B. 27a denotes a wire bonding portion of the source wiring.
Furthermore, a plan structure of a cell surrounded by the gate electrodes in the transistor cells is formed into an arbitrary shape such as a square, pentagon or hexagon. Moreover, in these transistors, they are often connected to an inductive load such as a motor. In this case, a reverse electromotive force might be applied when the operation is turned off. To prevent the transistors from being destroyed, such a method is adopted that the source electrode 27 is also connected to the channel diffusion region 22 as described above, whereby a reverse protection diode is formed between the source and the drain.
As set forth, in the MOSFET of the trench structure, the gate pad 25a connected to the gate wiring 29 is formed over the semiconductor layer surface through the gate oxide. Thus, it is positioned higher than the gate electrode 25 formed inside the recessed trench, and the gate pad 25a formed continuously to the gate electrode 25 is passed through a corner part of the recessed trench as indicated by A shown in FIG. 8C. Usually it is difficult to form an oxide film in a corner part and a resultant film becomes thinner in general, and thus problems arise such that the gate pad is short-circuited with the semiconductor layer, or gate voltage is dropped. On this account, the corner part undergoes a process called a rounding process, that is, a process for rounding the corner part in order to sufficiently deposit the gate oxide over the corner part as well. Even so, voltage cannot be enhanced enough. As for the process for rounding the corner part, a process in which sacrifice oxidation is performed to remove the oxide film in order to remove the semiconductor layer roughened after etching such as reactive ion etching; sacrifice oxidation is performed at a high temperature of about 1100xc2x0 C. (generally, about 900xc2x0 C.) to form a thick oxide film and remove it.
Additionally, in this type of semiconductor device, it is also necessary to sufficiently be protected from surges particularly.
Furthermore, it has been desired that signals can be transmitted to the surrounding transistor cells in low resistance without disposing the gate fingers, many cells can be formed as many as possible, and ON resistance can be reduced to realize heavy current.
Moreover, in the semiconductor device having many transistor cells of this type arranged in a matrix form, a problem arises that electric fields tend to concentrate on transistor cells around outside the cell region for easy destruction.
The present invention has been made to solve these problems. The purpose of the present invention is to provide a semiconductor device having a structure capable of sufficiently increasing gate voltage even in such a semiconductor device in which many transistor cells of a trench structure are formed in a matrix form and the gate electrodes thereof are contacted with a gate wiring formed of a metal film.
Another purpose of the present invention is to provide a semiconductor device having a structure that enhances voltage by a trench structure and is hardly broken down in case of a surge.
Still another purpose of the present invention is to provide a semiconductor device having a structure that reduces gate wirings as few as possible and allows signals to be transmitted to each of cells evenly.
Yet another purpose of the present invention is to provide a semiconductor device having a high-power MOSFET that enhances voltage by a trench structure, increases the number of cells as many as possible and realizes heavy current.
Yet another purpose of the present invention is to provide a semiconductor device having a structure where a depletion layer of a pn junction in a cell region is extended to the outer peripheral part of a chip to enhance voltage thereof enhanced even though a gate pad is formed inside a recessed part.
A semiconductor device according to the present invention has a semiconductor layer; a recessed trench formed in the semiconductor layer so as to arrange transistor cells of a trench structure in a matrix form; a gate electrode disposed inside the recessed trench through a gate oxide film; a gate pad disposed continuously to the gate electrode; and a gate wiring comprised of a metal film, the gate wiring disposed being contacted with the gate pad, wherein the gate pad is disposed inside a recessed part formed in the same depth of the recessed trench.
By this structure, the gate pad is formed at a low position inside the recessed part (so-called a sink pad). Thus, the gate electrode formed inside the recessed trench and the gate pad contacted with the gate wiring are continuously formed with no steps, and even the gate pad formed over the semiconductor layer surface through a thin gate oxide film is formed with the gate oxide film in firm thickness with no corners, allowing sufficiently high gate voltage to be obtained. Consequently, a semiconductor device having sufficiently high gate voltage can be obtained even in an insulated gate MOSFET of the trench structure.
When each of the transistor cells of the trench structure is a transistor having a structure in which a channel diffusion region of a conductivity type different from that of the semiconductor layer and a source region of the same conductivity type as that of the semiconductor layer are sequentially disposed vertically on the surface side of the semiconductor layer around the gate electrode, the surface of the source region is directly disposed with a source wiring formed of a metal film, and an alloy layer where the metal of the source wiring is spiked into the source region and the channel diffusion region to obtain Ohmic contact is formed, the area of a source electrode contact part can be reduced significantly, the number of transistor cells per unit area can be increased to a great extent, and a power MOSFET of a trench structure with high gate voltage, small ON resistance, and heavy current can be obtained.
A p-type layer and an n-type layer in a ring shape are alternately disposed on an insulating film on the outer peripheral side beyond the cell region, whereby a bi-directional protection diode is formed. Metal films having contact with the innermost and outermost layers of the p-type layer or n-type layer in a ring shape are formed, respectively. Each of the metal films having contact in a ring shape is deposited continuously to any one of the source wirings and the gate wirings formed of a metal film. Accordingly, a MOSFET of a stable trench structure can be formed in which the protection diode can be inserted between the source and the drain with small series resistance and surges can be released through the protection diode even though they are applied.
The gate wiring is disposed as having contact with the outermost layer of the protection diode, a gate connecting part is formed so that the gate wiring is partially stepped over the protection diode to be connected to the gate pad around the cell region, and the gate connecting part and a source connecting part having contact with the innermost layer of the source wiring are alternately formed in plan. Accordingly, the gate wiring connected to the protection diode in the outer periphery of the chip allows signal transmission to the gate electrodes throughout the cells without forming the gate wiring around the cell region.
A diffusion region having a conductivity type different from that of the semiconductor layer is formed around the outermost periphery of the cell region, and the source wiring contacted with the innermost layer of the protection diode is also brought into contact with the diffusion region. Accordingly, a depletion layer is extended to the outer side of the diffusion region, and the cells in the outermost periphery can be protected, which are easy to break.
The gate pad disposed inside the cell region or around the outer periphery thereof is intermittently separated, the recessed part is not formed in the portion which the gate pad is not formed, a diffusion region comprised of a conductivity type different from that of the semiconductor layer is formed over the semiconductor layer surface, and the diffusion region allows the depletion layer formed between the channel diffusion region formed in each of the transistor cells and the semiconductor layer to be extended on the outer peripheral side of the semiconductor chip. Accordingly, even though the recessed part is formed for gate pad formation and a sallow diffusion region formed of the same conductivity type as that of the channel diffusion region is lost, a well region is formed to the end part side of the semiconductor chip through the gate electrode on the adjacent side of the channel diffusion region or source region in the transistor cells, for example, and thus the depletion layer formed between the channel diffusion region and the semiconductor layer can be extended to the end part side of the semiconductor chip, allowing voltage to be enhanced. On the other hand, the gate pad is formed in a portion where the gate electrode is extended straight. Therefore, it is formed inside the recessed part continuously to the gate electrode, and is connected to the gate wiring contacted thereon, with no interference in signal transmission to the gate electrodes.
A diffusion region formed of the same conductivity type as that of the channel diffusion region of the transistor cells is formed under the gate pad disposed inside the cell region or around the outer periphery thereof, deeper than the channel diffusion region of the transistor cells. Accordingly, even though the gate pad is formed inside the recessed part, a well region is formed under the recessed part, and the depletion layer can be extended to the end part side of the semiconductor chip.